How SPLat works: Architecture

The following is something you may never need to know, but you may find it interesting. (If it sounds like techno-babble, don't worry. This is not the kind of thing you need to understand to use SPLat!)

The SPLat processor is a virtual machine (VM) implemented in a general purpose microcontroller. Older designs in the current product line-up use an 8-bit Freescale 9S08 family chip, with all the firmware written in assembler. Recent designs (starting 2012) use a variety of 32-bit ARM processor chips with firmware written in C/C++. The VM architecture is based on an 8-bit wide by 4 deep register stack (slightly akin to Forth). It has separate program and data (RAM) memory spaces with 16 bit and 8 bit addresses respectively. Current products expose (depending on the model) up to 64,000 bytes of FLASH program memory and 250 bytes of RAM.

There is a separate 6-deep x 16 bit subroutine return stack, and an 8-bit index register for advanced RAM addressing. The floating point processor contains two 32-bit floating point registers, and implements non-stop arithmetic (e.g. a divide by zero will not crash the processor). Recent ARM based designs contain floating point hardware.

Additional intrinsic functionality is provided by built in counters. Depending on the product model there are

• One 24-bit high speed hardware counter capable of pulse count and frequency.
• Eight 16-bit medium speed counters with pulse and frequency
• One or more 24-bit bidirectional quadrature counters

MultiTrack provides a very effective and processor-efficient cooperative multitasking system. A task queue is implemented using a fixed number of static entries. Each entry stores execution address, pointers and timer information. By not saving registers we extract the maximum use from a small amount of RAM and make context switching extremely fast. As it turns out, the kinds of control tasks SPLat is aimed at are better off with these efficiencies than with resource consuming full-context saving, preemption and task prioritization. The result is a system with 70 microsecond context switching time at 8MHz bus speed. Light, and very nimble! (The 32 bit designs are introducing a separate register set, including the subroutine return stack, per task, and other architectural improvements we couldn't do in the resource limited 8-bit chips.)

For communicating with various peripherals SPLat contains a 20-byte register called U and an associated 1-byte register called V (which holds byte counts for U). U and V act as a transfer buffer for peripheral devices built within the SPLat Expansion Framework.

A separate background subsystem provides external communications, with support for:

• SPLatLink, our own protocol that's used mainly for debugging and program download
• ModBus RTU Master
• ModBus RTU Slave
• "User" protocol, which lets you program to handle typical 3rd party devices that use serial ASCII data, such as motion control boards or weighers.
• SimpleHMI, a very easy to program Human Machine Interface